After this masterclass, you:

• Understand the fundamentals of the RISC-V architecture
• Understand the fundamentals of the RISC-V programming tool chain and will be able to use it
• Have learned about the state of the art in attacks against RISC-V
• Have learned about the state of the art of protections in RISC-V
• Understand the concepts of Instruction Set Extension by means of an example

• Cryptography and security researchers that need to use RISC-V for their research or applications
• Designers, developers, or any users that want to use or get familiar with RISC-V and its opportunities for secure applications
• IoT, Cyber-Physical systems and Security enthusiasts

Knowledge about the principles of computer architecture and software programming is required. Knowledge about Verilog or VHDL is useful, but not necessary to understand the principles and explanations.

Participants will benefit from our strong academic and industrial experience in the field of architecture for security and processor customization for security.  In this masterclass, you will learn about the RISC-V architecture for security applications in a self-contained fashion.

Dr. Francesco Regazzoni received his Master of Science degree from Politecnico di Milano and his PhD degree from Università della Svizzera italiana.  He held research positions at the Université Catholique de Louvain and at Technical University of Delft, and has been visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, and EPFL Lausanne and NTU Singapore.

His research interests are mainly focused on secure IoT devices and embedded systems, covering in particular design automation for security, physical attacks and countermeasures, post-quantum cryptography, and efficient implementation of cryptographic primitives.