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Hardware Security: RISC-V for Security Applications

Do you want to learn about the fundamentals of the RISC-V architecture, how to implement security primitives on it, and how to customize it to your needs? Do you want to take full advantage of an open processor platform for your security applications? This self-contained 1-day master class explains the basics of the RISC-V architecture and will present examples of its use for security applications.

RISC-V and Hardware Security

The rise of RISC-V brought new opportunities for designers and engineers that need security. RISC-V can, in fact, be modified and extended to provide advanced security features or to accelerate specific cryptographic algorithms. In this course, after an introduction to the fundamentals of the RISC-V architecture and a demonstration of a tool chain to use it, you will learn the most common attacks that are targeting the platform and the main mechanisms to counteract these threats. You will also familiarize with the concept of instruction set extension and you will learn how it can be used to enhance the security functionalities of RISC-V.

Why choose this masterclass?
  • Learning objectives

    After this masterclass, you:

    • Understand the fundamentals of the RISC-V architecture
    • Understand the fundamentals of the RISC-V programming tool chain and will be able to use it
    • Have learned about the state of the art in attacks against RISC-V
    • Have learned about the state of the art of protections in RISC-V
    • Understand the concepts of Instruction Set Extension by means of an example
  • Whom is this masterclass suitable for?
    • Cryptography and security researchers that need to use RISC-V for their research or applications
    • Designers, developers, or any users that want to use or get familiar with RISC-V and its opportunities for secure applications
    • IoT, Cyber-Physical systems and Security enthusiasts

    Knowledge about the principles of computer architecture and software programming is required. Knowledge about Verilog or VHDL is useful, but not necessary to understand the principles and explanations.

  • What makes this masterclass unique?

    Participants will benefit from our strong academic and industrial experience in the field of architecture for security and processor customization for security.  In this masterclass, you will learn about the RISC-V architecture for security applications in a self-contained fashion.

  • Lecturer: Dr. Francesco Regazzoni

    Dr. Francesco Regazzoni received his Master of Science degree from Politecnico di Milano and his PhD degree from Università della Svizzera italiana.  He held research positions at the Université Catholique de Louvain and at Technical University of Delft, and has been visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, and EPFL Lausanne and NTU Singapore.

    His research interests are mainly focused on secure IoT devices and embedded systems, covering in particular design automation for security, physical attacks and countermeasures, post-quantum cryptography, and efficient implementation of cryptographic primitives.

Practical Information

Date: Will be announced as soon as possible
Mode of study: Onsite programme
Certificate: A Certificate of Attendance from the University of Amsterdam
Maximum number of participants: 20
Price: € 995,- (UvA alumni get a 10% discount. Fees are VAT-exempt)
Location: Lab42, Science Park 900, Amsterdam 
Language: English
Study materials: Will be provided on the days of the masterclass.
Required software: Participants are encouraged to bring their laptop, but the core part course can be followed even without it. No programmes need to be installed beforehand, but it is useful to have the right to install something on your laptop if needed.


Do you have questions about this masterclass?
Please contact Liza Lambert, Project Manager Lifelong Learning (Informatics Institute)

Facts & Figures
Language of instruction
Science Park